1. Field of the Invention
The present invention relates to a wireless receiver apparatus, and in particular, to a wireless receiver apparatus including a gain control amplifier (GCA), and a semiconductor integrated circuit which is formed by integrating a circuit of the wireless receiver apparatus.
2. Description of the Related Art
FIG. 9 is a block diagram showing a configuration of a wireless receiver apparatus used in, for example, a wireless communication system of a personal handy-phone system (hereinafter referred to as PHS) according to a prior art, and FIG. 10 is a block diagram showing a configuration of a frequency converter and intermediate frequency circuit 3A of FIG. 9.
Referring to FIG. 9, the wireless receiver apparatus of the prior art is configured by including an antenna 1, a high frequency amplifier circuit 2, the frequency converter and intermediate frequency circuit 3A and a demodulator 4. A wireless signal received by the antenna 1 is low-noise-amplified by the high frequency amplifier circuit 2, and then, it is inputted to the frequency converter and intermediate frequency circuit 3A. An alternative configuration may be provided, in which the output signal from the high frequency amplifier circuit 2 is low-noise-amplified and then it is outputted to the frequency converter and intermediate frequency circuit. The frequency converter and intermediate frequency circuit 3A performs intermediate frequency amplification having a low frequency conversion function to process the inputted wireless signal into a predetermined intermediate frequency signal and an automatic gain control (hereinafter referred to as AGC) function, and then, outputs the processed intermediate frequency signal to the demodulator 4. The demodulator 4 demodulates the inputted intermediate frequency signal into an audio signal and a baseband signal of data and so on by a predetermined demodulation system, and then, outputs the resulting signals.
Referring to FIG. 10, the frequency converter and intermediate frequency circuit 3A is configured by including an input terminal 100, a mixer 101, a band-pass filter (BPF) 102, a gain control amplifier (GCA) 103, a band-pass filter (BPF) 104, an output terminal 105, a PLL (Phase Locked Loop) circuit 200, a three-line bus 201 for channel setting, a shift register and latch circuit 202, an RSSI (Received Signal Strength Identifier) detector circuit 300, a hold capacitor 301 for holding an RSSI detection voltage, a voltage follower circuit 302 for impedance conversion, comparators 303 and 303A, threshold voltage sources 303a and 303b, an AGC selection circuit 304 including switches 304a and 304b and an AGC control logic circuit 311.
FIG. 4 is a graph showing an input signal level to bit error rate (BER) characteristic in the frequency converter and intermediate frequency circuit 3A of FIG. 10 of the prior art. It is noted that the gain of the AGC control logic circuit 311 is switched at the boundaries of adjoining regions of a high-gain region, a medium-gain region and a low-gain region in the AGC control logic circuit 311 of FIG. 10.
FIG. 6A is a timing chart showing a response characteristic of the RSSI voltage with respect to reception data when an 8PSK wireless signal having a field strength in the vicinity of a threshold voltage VTHtr of the comparator 303 in the frequency converter and intermediate frequency circuit 3A of FIG. 10, and FIG. 6B is an enlarged timing chart of a portion 601 of FIG. 6A. In this case, the 8PSK wireless signal means a wireless signal modulated by 8-phase PSK. FIG. 7A is a timing chart showing a response characteristic of the RSSI voltage with respect to reception data when a π/4QPSK wireless signal having a field strength in the vicinity of the threshold voltage VTHtr of the comparator 303 in the frequency converter and intermediate frequency circuit 3A of FIG. 10, and FIG. 7B is an enlarged timing chart of a portion 602 of FIG. 7A. In this case, the π/4QPSK wireless signal means a wireless signal modulated by QPSK with a shift of π/4.
Referring to FIG. 6, it has been confirmed that, when the gain of the gain control amplifier 103 is switched by the operation of the AGC control logic circuit 311 of FIG. 10 not for the interval of a start symbol (SS), a preamble (PR) and a unique word (UW) of the header data part but for the interval of the actually received data part of the data signal demodulated from the received wireless signal, partial data of the actually received data part at the time of switching drops out and a bit error rate (BER) deteriorates (See 501 and 502 of FIG. 4). As a countermeasure, the above phenomenon has been conquered by switching the gain of the gain control amplifier 103 for the interval of the unique word (UW) of the header data part by changing the constant of the hold capacitor 301 for holding the RSSI detection voltage to change the time constant. That is, as shown in FIG. 7, the amounts 6f ripples in the unique word (UW) and the data scarcely vary even with ripples in the RSSI voltage, the gain of the gain control amplifier 103 can be switched for the interval of the unique word (UW) of the header data part.
Moreover, the Japanese patent laid-open publication No. JP 2004-23708-A discloses a wireless terminal apparatus for suppressing an offset voltage that rapidly varies in accordance with a gain control signal in a direct conversion receiver and the wireless terminal apparatus that includes the receiver. In the wireless terminal apparatus, a dummy offset generator circuit generates a dummy offset voltage in accordance with the voltage detected from an output node of a variable gain amplifier and the gain control signal, and a dummy variable gain amplifier generate an offset cancellation voltage by amplifying the dummy offset voltage in accordance with the gain control signal, and outputs the offset cancellation voltage to the output node of the variable gain amplifier, and this leads to cancellation of the offset voltage component from the output signal of the variable gain amplifier.
However, there has recently been a mode in which the modulation systems of the header data part and the real data part change with the advance of data transfer. For example, in an upgradable system of a PHS wireless system, the header data part is modulated by π/4QPSK modulation, and the real data part is modulated by 8PSK modulations. In such a mode, the amount of ripples in a field strength detection current outputted from the RSSI detector circuit 300 differs in the header data part and the real data part. Even when the constant of the hold capacitor 301 of the prior art is optimized, the gain of the gain control amplifier is disadvantageously varied for the interval of the real data part at an input level in the vicinity of the field strength with which the gain of the gain control amplifier 103 varies, and the bit error rate (BER) deteriorates as shown in FIG. 4, and this leads to deterioration in the conversation quality. It is noted that the problem could not be solved also in the wireless terminal apparatus disclosed in the Japanese patent lad-open publication No. JP 2004-23708-A.